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d a t a sh eet preliminary speci?cation supersedes data of 1998 feb 25 file under integrated circuits, ic02 1998 aug 26 integrated circuits tda8768 12-bit high-speed analog-to-digital converter (adc)
1998 aug 26 2 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 features 12-bit resolution sampling rate up to 55 mhz - 3 db bandwidth of 190 mhz 5 v power supplies binary or twos-complement cmos outputs in-range cmos-compatible output tll-cmos compatible static digital inputs 3 to 5 v cmos-compatible digital outputs differential clock input; positive emitter coupled logic (pecl)-compatible power dissipation 325 mw (typical) low analog input capacitance (typical 2 pf), no buffer amplifier required integrated sample-and-hold amplifier differential analog input external amplitude range control voltage controlled regulator included. applications high-speed analog-to-digital conversion for C video signal digitizing C high definition tv (hdtv) C imaging (camera scanner) C medical imaging C telecommunication C base-station receiver. general description the tda8768 is a bipolar 12-bit analog-to-digital converter (adc) optimized for telecommunications and professional imaging. it converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 55 mhz. all static digital inputs (sh, ce and otc) are ttl and cmos compatible and all outputs are cmos compatible. a sine wave clock input signal can also be used. quick reference data ordering information symbol parameter conditions min. typ. max. unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 5.25 v i cca analog supply current - 33 tbf ma i ccd digital supply current - 30 tbf ma i cco output supply current f clk = 4 mhz; f i = 400 khz - 3.2 tbf ma inl integral non-linearity f clk = 4 mhz; f i = 400 khz - 2.0 4.5 lsb dnl differential non-linearity f clk = 4 mhz; f i = 400 khz - 0.6 1.0 lsb f clk(max) maximum clock frequency tda8768h/4 40 -- mhz tda8768h/5 55 -- mhz p tot total power dissipation - 325 tbf mw type number package sampling frequency (mhz) name description version tda8768h/4 qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 40 tda8768h/5 55
1998 aug 26 3 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 block diagram fig.1 block diagram. v i handbook, full pagewidth mgr470 d11 msb data outputs 19 21 d10 22 d9 23 d8 24 d7 25 d6 26 d5 27 d4 d3 28 29 43 42 39 11 1, 5 to 8, 12 to 14, 16 v ref sh n.c. d2 30 d1 31 d0 lsb 32 v cco 33 ir 34 20 18 cmos outputs latches analog-to-digital converter clock driver 15 v ccd2 37 v ccd1 41 v cca4 3 v cca3 9 v cca2 2 v cca1 36 clk 35 clk cmos output ognd overflow/ underflow latch ce otc amp sample- and-hold tda8768 17 dgnd2 38 dgnd1 40 agnd4 4 agnd3 10 agnd2 44 agnd1 v i
1998 aug 26 4 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 pinning symbol pin description n.c. 1 not connected v cca1 2 analog supply voltage 1 (+5 v) v cca3 3 analog supply voltage 3 (+5 v) agnd3 4 analog ground 3 n.c. 5 not connected n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected v cca2 9 analog supply voltage 2 (+5 v) agnd2 10 analog ground 2 v ref 11 reference voltage input n.c. 12 not connected n.c. 13 not connected n.c. 14 not connected v ccd2 15 digital supply voltage 2 (+5 v) n.c. 16 not connected dgnd2 17 digital ground 2 otc 18 control input twos complement output; active high ce 19 chip enable input (cmos level; active low) ir 20 in-range output d11 21 data output; bit 11 (msb) d10 22 data output; bit 10 d9 23 data output; bit 9 d8 24 data output; bit 8 d7 25 data output; bit 7 d6 26 data output; bit 6 d5 27 data output; bit 5 d4 28 data output; bit 4 d3 29 data output; bit 3 d2 30 data output; bit 2 d1 31 data output; bit 1 d0 32 data output; bit 0 (lsb) v cco 33 output supply voltage (3 to 5.25 v) ognd 34 output ground clk 35 complementary clock input; active low clk 36 clock input v ccd1 37 digital supply voltage 1 (+5 v) dgnd1 38 digital ground 1 sh 39 sample-and-hold enable input (cmos level; active high) agnd4 40 analog ground 4 v cca4 41 analog supply voltage 4 (+5 v) v i 42 positive analog input voltage v i 43 negative analog input voltage agnd1 44 analog ground 1 symbol pin description
1998 aug 26 5 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 fig.2 pin configuration. handbook, full pagewidth tda8768h mgr469 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 n.c. n.c. n.c. n.c. n.c. v cca1 v cca3 v cca2 v ref agnd3 agnd2 n.c. n.c. n.c. n.c. ir d11 d10 dgnd2 v ccd2 ce otc d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ognd dgnd1 agnd4 agnd1 v ccd1 v cca4 clk v cco clk sh v i v i
1998 aug 26 6 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. the supply voltages v cca , v ccd and v cco may have any value between - 0.3 v and +7.0 v provided that the supply voltage differences d v cc are respected. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter conditions min. max. unit v cca analog supply voltage note 1 - 0.3 +7.0 v v ccd digital supply voltage note 1 - 0.3 +7.0 v v cco output supply voltage note 1 - 0.3 +7.0 v d v cc supply voltage difference v cca - v ccd - 1.0 +1.0 v v ccd - v cco - 1.0 +4.0 v v cca - v cco - 1.0 +4.0 v v i input voltage at pins 42 and 43 referenced to agnd 0.3 v cca v v i(p-p) input voltage at pins 35 and 36 for differential clock drive (peak-to-peak value) - v ccd v i o output current - 10 ma t stg storage temperature - 55 +150 c t amb operating ambient temperature - 10 +85 c t j junction temperature - 150 c symbol parameter condition value unit r th(j-a) thermal resistance from junction to ambient in free air 75 k/w
1998 aug 26 7 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 characteristics v cca =v 2 to v 44 , v 9 to v 10 , v 3 to v 4 and v 41 to v 40 = 4.75 to 5.25 v; v ccd =v 37 to v 38 and v 15 to v 17 = 4.75 to 5.25 v; v cco =v 33 to v 34 = 3.0 to 5.25 v; agnd and dgnd shorted together; t amb = 0 to 70 c; typical values measured at v cca =v ccd = 5 v and v cco = 3.3 v, t amb =25 c, v i(p-p) - v i(p-p) = 2.0 v and c l = 10 pf; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 5.25 v i cca analog supply current - 33 45 ma i ccd digital supply current - 30 37 ma i cco output supply current f clk = 4 mhz; f i = 400 khz - 3.2 tbf ma f clk = 40 mhz; f i = 4.43 mhz - 11 tbf ma inputs clk and clk ( referenced to dgnd) v il low-level input voltage v ccd = 5 v; note 1 3.19 - 3.52 v v ih high-level input voltage v ccd = 5 v; note 1 3.83 - 4.12 v i il low-level input current v clk or v clk = 3.19 v - 10 -- m a i ih high-level input current v clk or v clk = 3.83 v -- 10 m a z i input impedance f clk = 40 mhz 2 -- k w c i input capacitance f clk = 40 mhz -- 2pf d v clk(p-p) differential ac input voltage (peak-to-peak value) for switching (v clk - v clk ) dc voltage level = 2.5 v 0.5 - 2.0 v otc, sh and ce ( referenced to dgnd); see tables 1 and 2 v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2.0 - v ccd v i il low-level input current v il = 0.8 v - 20 -- m a i ih high-level input current v ih = 2.0 v -- +20 m a v i and v i ( referenced to agnd); v ref =v cca - 1.825 v; see table 1 i il low-level input current - 10 -m a i ih high-level input current - 10 -m a r i input resistance f i = 4.43 mhz 100 -- k w c i input capacitance f i = 4.43 mhz -- 2pf v i(cm) common mode input voltage v i = v i ; output code 2047 v cca = 5 v tbf 3.6 tbf v v cca = 4.75 v tbf 3.35 tbf v v cca = 5.25 v tbf 3.85 tbf v
1998 aug 26 8 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 voltage controlled regulator input v ref (referenced to agnd); note 2 v ref(fs) full-scale ?xed voltage v cca =5v - 3.175 - v i ref input current - 0.5 10 m a v i(p-p) - v i(p-p) input voltage amplitude (peak-to-peak value) v ref =v cca - 1.825 v - 2.0 - v outputs (referenced to ognd) d igital outputs d11 to d0 and ir ( referenced to ognd) v ol low-level output voltage i ol = 2 ma 0 - 0.5 v v oh high-level output voltage i oh = - 0.4 ma v cco - 0.5 - v cco v i o output current in 3-state output level between 0.5 v and v cco - 20 - +20 m a switching characteristics c lock frequency f clk ; see fig.3 f clk(min) minimum clock frequency sh = high -- 2 mhz f clk(max) maximum clock frequency tda8768h/4 40 -- mhz tda8768h/5 55 -- mhz t clkh clock pulse width high 8.5 -- ns t clkl clock pulse width low 8.5 -- ns analog signal processing; 50% clock duty factor; v i - v i = 2.0 v; v ref =v cca - 1.825 v; see table 1 l inearity inl integral non-linearity f clk = 4 mhz; f i = 400 khz - 2.0 4.5 lsb dnl differential non-linearity f clk = 4 mhz; f i = 400 khz; no missing code - 0.6 1.0 lsb e offset offset error v cca =v ccd =v cco =5v; t amb =25 c; v i = v i ; output code = 2047 tbf - 11 tbf mv e g(fs) gain error amplitude (full scale); spread from device to device v cca =v ccd =v cco =5v; t amb =25 c; v i(p-p) - v i(p-p) = 2.0 v - 5 - +5 % b andwidth (f clk = 55 mhz); note 3 b analog bandwidth - 3 db; full scale input tbf 190 - mhz h armonics (f clk = 40 mhz) h fund(fs) fundamental harmonics (full scale) f i = 4.43 mhz -- 0db h tot(fs) harmonics (full scale); all components f i = 4.43 mhz second harmonic -- 75 - db third harmonic -- 70 - db thd total harmonic distortion f i = 4.43 mhz; note 4 -- 66 - db symbol parameter conditions min. typ. max. unit
1998 aug 26 9 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 t hermal noise n th(rms) thermal noise (rms value) grounded input; f clk = 40 mhz - 0.25 tbf lsb s purious free dynamic range dr sf spurious free dynamic range f i = 4.43 mhz tbf 69 - db f i = 10 mhz tbf tbf - db f i = 20 mhz tbf tbf - db s ignal - to - noise ratio ; note 5 s/n signal-to-noise ratio without harmonics; f clk = 40 mhz; f i = 4.43 mhz - 67 - db e ffective number of bits ; note 5 n bit effective number of bits tda8768h/4 (f clk = 40 mhz) f i = 4.43 mhz - 10.3 - bits f i =10mhz - tbf - bits f i =15mhz - tbf - bits effective number of bits tda8768h/5 (f clk = 55 mhz) f i = 4.43 mhz - 9.9 - bits f i =10mhz - tbf - bits f i =15mhz - tbf - bits f i =20mhz - tbf - bits i ntermodulation ; note 6 ttir two-tone intermodulation rejection f clk = 40 mhz tbf 66 - db d 3 third order intermodulation distortion f clk = 40 mhz tbf 67 - db b it error rate ber bit error rate f clk = 40 mhz; f i = 4.43 mhz; v i = 16 lsb at code 2047 - 10 - 15 tbf times/ sample timing (c l = 10 pf); see fig.3 and note 7 t d(s) sampling delay time -- 2ns t h output hold time 4 -- ns t d output delay time v cco = 5.25 v - 10 15 ns v cco = 3.0 v 13 18 ns 3-state output delay times; see fig.4 t dzh enable high - 14 18 ns t dzl enable low - 16 20 ns t dhz disable high - 16 20 ns t dlz disable low - 14 18 ns symbol parameter conditions min. typ. max. unit
1998 aug 26 10 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 notes 1. the circuit has two clock inputs: clk and clk. there are four modes of operation: a) pecl mode 1: (dc level varies 1 : 1 with v ccd ) clk and clk inputs are at differential pecl levels. b) pecl mode 2: (dc level varies 1 : 1 with v ccd ) clk input is at pecl level and sampling is taken on the falling edge of the clock input signal. a dc level of 3.65 v has to be applied on clk decoupled to gnd via a 100 nf capacitor. c) pecl mode 3: (dc level varies 1 : 1 with v ccd ) clk input is at pecl level and sampling is taken on the rising edge of the clock input signal. a dc level of 3.65 v has to be applied on clk decoupled to gnd via a 100 nf capacitor. d) ac driving mode 4: when driving the clk input directly and with any ac signal of minimum 0.5 v (peak-to-peak value) and with a dc level of 2.5 v, the sampling takes place at the falling edge of the clock signal. when driving the clk input with the same signal, sampling takes place at the rising edge of the clock signal. it is recommended to decouple the clk or clk input to dgnd via a 100 nf capacitor. 2. it is possible with an external reference connected to pin v ref to adjust the adc input range. this voltage has to be referenced to v cca . for v cca - 1.825 v, the differential input voltage amplitude is 2 v (peak-to-peak value). 3. the - 3 db analog bandwidth is determined by the 3 db reduction in the reconstructed output, the input being a full-scale sine wave. 4. thd (total harmonic distortion) is obtained with the addition of the first five harmonics: where f is the fundamental harmonic referenced at 0 db for a full-scale sine wave input. 5. effective number of bits are obtained via a fast fourier transform (fft). the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to snr: snr = n bit 6.02 + 1.76 db. 6. intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 mhz. the two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter ( - 6db below full-scale for each input signal). d 3 is the ratio of the rms value of either input tone to the rms value of the worst case third order intermodulation product. 7. output data acquisition: the output data is available after the maximum delay of t d . thd 20 log f (2nd) 2 (3rd) 2 (4th) 2 (5th) 2 (6th) 2 ++++ --------------------------------------------------------------------------------------------------------------- =
1998 aug 26 11 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 table 1 output coding with differential inputs (typical values to agnd); v i(p-p) - v i(p-p) = 2.0 v; v ref =v cca - 1.825 v table 2 mode selection note 1. x = dont care. table 3 sample-and-hold selection code v i(p-p) v i(p-p) ir binary outputs twos complement outputs d11 to d0 d11 to d0 under?ow <3.1 >4.1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3.1 4.1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 -- 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 -- 2047 3.6 3.6 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- 4094 -- 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 4095 4.1 3.1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 over?ow >4.1 <3.1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 otc ce d0 to d11 and ir 0 0 binary; active 1 0 twos complement; active x (1) 1 high impedance sh sample-and-hold 1 active 0 inactive; tracking mode
1998 aug 26 12 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 fig.3 timing diagram. handbook, full pagewidth sample n + 1 sample n clk mgr472 sample n + 2 v i data d0 to d11 t h t d t ds t clkh t clkl high low 50 % high low 50 % data n + 1 data n data n - 1 data n - 2 fig.4 timing diagram and test conditions of 3-state output delay time. f ce = 100 khz. handbook, full pagewidth mbg856 50 % 50 % high low t dzh t dhz 50 % high low t dzl t dlz 10 % 90 % output data 0 v v ccd output data 3.3 k w 15 pf s1 v ccd tda8768 ce ce test dlz t dzl t dhz t dzh s1 ccd v ccd v dgnd dgnd t
1998 aug 26 13 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 application information fig.5 application diagram. the analog, digital and output supplies should be separated and decoupled. (1) single-ended clock signals can be applied if required. (2) r1 and r2 must be determined in order to obtain a middle voltage of 3.6 v; see common mode input voltage. in addition, to ensure a sufficient analog input stability, the minimum current into these resistors must be approximately 1 ma. (3) v ref must be decoupled to v cca . handbook, full pagewidth mgr471 1 2 3 4 5 6 7 8 9 10 11 12 n.c. n.c. n.c. n.c. 13 14 15 16 17 18 19 20 21 22 ir d11 (msb) d10 tda8768 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 26 25 24 23 27 d2 d1 d0 (lsb) 5 v d3 d4 d5 d6 d7 d8 d9 100 nf 5 v 100 nf 100 nf 100 nf output format select chip select input 5 v 100 nf v ref (3) 5 v n.c. n.c. n.c. n.c. n.c. clk clk 100 nf 100 nf 5 v 5 v sh mode (2) (1) v i v i 100 w 100 w r1 v cca r2 4.7 m f 10 nf 220 nf input 1 : 1
1998 aug 26 14 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 fig.6 application diagram for differential clock input (pecl-compatible) using a ttl to pecl translator. if the clock lines are more than 1 inch long they must be matched. in fact, the 27 w resistor will be changed by the series connection of r1 and r2, with r1 = z o placed close to pins clk and clk. (1) 50 w matched line (z o , l). handbook, full pagewidth mgl474 tda8768 translator pecl clk clk 35 36 d (1) 270 w 270 w 100 nf 100 nf z0 = 50 w z0 = 50 w r1 500 w r1 500 w r2 220 w r2 220 w ttl input fig.7 application diagram for differential clock input (pecl-compatible) using a ttl to pecl translator and thevenin parallel terminations. the value of r1 and r2 must be chosen in order to meet the following relations: and (1) 50 w matched line (z o , l). 3v v ccd r2 r1 r2 + ---------------------------- - = z0 r1 r2 r1 r2 + ---------------------- = handbook, full pagewidth mgl473 tda8768 translator pecl clk clk 35 36 d v ccd (1) r2 120 w r2 120 w 100 nf r1 82 w r1 82 w ttl input
1998 aug 26 15 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1998 aug 26 16 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all qfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 aug 26 17 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1998 aug 26 18 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 notes
1998 aug 26 19 philips semiconductors preliminary speci?cation 12-bit high-speed analog-to-digital converter (adc) tda8768 notes
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philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 545104/750/02/pp20 date of release: 1998 aug 26 document order number: 9397 750 03378

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